1. Field of the Invention
The invention relates to a method of fabricating a dynamic random memory (DRAM), and more particularly to a method of fabricating a DRAM by using field implantation and anti-punch through implantation.
2. Description of the Related Art
As the function of computer and electronic products becomes more and more advanced, the applied circuit grows more and more complex. Based on the consideration of fabrication cost and stability, the density of devices in every single integrated circuit (IC) is demanded greatly. However, to achieve a very high density of devices on an IC, in addition to the shrinkage of the device size, the layout has to be altered proportionally. Therefore, both the limitation of a design rule and the physical characteristics of devices are to be considered.
In a metal-oxide-semiconductor (MOS), the channel width is not reduced unlimitedly. When the channel width is reduced to a certain degree, a short channel effect and a punch through phenomenon occur. To overcome the short channel effect, a lightly doped drain (LDD) structure is adapted. To solve the problem of punch through, a punch through implantation is perform to obtain a higher punching through voltage.
Referring to FIG. 1A to FIG. 1D, a conventional method of fabricating a DRAM is shown. In FIG. 1A, on a semiconductor substrate 100, for example, a P-type semiconductor, a pad oxide layer 102 is formed. A silicon nitride layer 104 is formed on the pad oxide layer 102, and a photo-resist layer 106 is formed on the silicon nitride layer 104.
In FIG. 1B, using photolithography and etching, the photo-resist layer 106 is patterned as 106a to defined an active region 142 on a memory cell region 140 and an active region and 152 on a periphery circuit region 150. Using the photo-resist layer 106a as a mask, the exposed silicon nitride layer 104 is removed to expose the pad oxide layer 102. The remaining silicon nitride layer 104a is shown as figure. Again, using the photo-resist layer 106a as a mask, field implanted regions 108 and 109 in the memory cell region 140 and the periphery circuit region 150 respectively are formed by field implantation or channel stop implantation 103. For example, the field implantation or channel stop implantation is performed with boron ions of about 6.times.10.sup.12 ion/cm.sup.2 at about 150 KeV.
In FIG. 1C, the photo-resist layer 160a is removed. The remaining silicon nitride layer 104a is used as a mask for thermal oxidation in an environment with mist. The exposed pad oxide layer 102 is transformed as a field oxide layer 112 by thermal oxidation. During thermal oxidation, the implanted ions are driven in the substrate 100 to enhance the device isolation effect.
Referring to FIG. 1D, the remaining silicon nitride layer 104a and the pad oxide layer 102 are removed. Hitherto, a local oxidation of silicon (LOCOS) is performed. A protective thin oxide layer 102a is formed on the active regions 142 and 152. Anti-punch through implanted region 118 and 119 are formed in the memory cell region 140 and the periphery circuit region 150 by anti-punch through ion implantation 105. The ion implantation 105 is performed, for example, with P-type boron ions of about 4.times.10.sup.12 ion/cm.sup.2 at about 150 KeV. The punch through voltage of a DRAM is increased by increasing the doping concentration under the channel.
In FIG. 1E, a transfer transistor 126, a capacitor 128, and a periphery circuit 130 are formed by a conventional method.
As the integration of a semiconductor devices increases, the design rule reduces. The above field implantation is performed with a shrinking linewidth. A narrow width effect happens due to field implantation, so that the threshold voltage is increased.
FIG. 2A to FIG. 2C shows another conventional method of fabricating a DRAM. Referring to FIG. 2A, on a semiconductor substrate 200, for example, a P-type substrate, a field oxide layer 212 is formed to isolate device region. The field oxide layer 212 is formed, for example, by LOCOS. Simultaneously, channel stops 208 and 209 are formed in a predetermined memory cell region 240 and a predetermined periphery circuit region 250 respectively by field implantation 203. The field implantation is performed with boron ions of about 4.times.10.sup.12 ion/cm.sup.2 at about 70 KeV.
In FIG. 2C, a transfer transistor 226, a capacitor 228, and a periphery circuit 230 are formed by a conventional method.
The narrow channel effect in the process with reduced linewidth is prevented by the above method. However, according to design rule, the ion dosages of field implantation in the memory cell region and in the periphery circuit region are different. It is found that the ion dosages in the memory cell region and the periphery circuit region are the same by the above method. Using higher ion dosage of field implantation for the periphery circuit region, the potential difference of the source/drain region (junction area) of the field effect transistor in the memory cell region is increased. The electric field effect is enhanced, and a serious leakage current from the capacitor of the memory cell region occurs. The shortage of storage charges in the capacitor causes a shorter refresh time to ensure the correctness of data access. On the other hand, using lower ion dosage of field implantation for the memory cell region, a required concentration of in the field oxide region of the periphery circuit region cannot be obtained to achieve channel stop effect.